System‑Level Protection Design for DC Power Input in Hardware Circuit Design

In hardware circuit design, protection for DC power input terminals is often simplified into the single‑sided idea of "installing one fuse in series". However, practical engineering experience shows that many devices work normally under laboratory conditions, yet frequently reboot or even burn out once deployed on‑site. The root cause lies in the lack of systematic coordinated design for front‑end protection. Genuine input protection is not a simple stack of isolated components. Instead, a multi‑level, multi‑mechanism cooperative defense system should be built to handle different abnormal operating conditions with layered protection strategies.

1. Fuse Selection: Dual Constraints of I²t Value and Breaking Capacity

Fuse selection is far more than checking rated current only. Both energy withstand capability and breaking limit must be evaluated comprehensively.

I²t value (Joule integral): This parameter defines the thermal energy threshold required for fuse blowing. During power‑on of capacitive loads or motor startup, high‑amplitude surge current occurs in circuits. If the I²t rating of the fuse is lower than this non‑destructive surge energy, nuisance tripping will take place. During component selection, make sure the fuse I²t value exceeds actual surge energy, and a 20%‑25% derating safety margin is recommended.

Breaking capacity: In severe short‑circuit faults, when short‑circuit current exceeds the safe cut‑off limit of the fuse, continuous arcing or even fire hazards may occur. Especially for battery packs or low‑internal‑resistance power supply systems, fuses with high breaking capacity (such as Class T series with 200kA breaking capacity at 125V DC) must be adopted. Ordinary glass‑tube fuses shall never be used in such high‑current scenarios.

2. TVS Diode Selection: Hidden Pitfall of Clamping Voltage

TVS diodes are widely used to suppress transient impacts such as ESD and EFT. Nevertheless, designers often fall into parameter‑selection traps. Many engineers only focus on reverse stand‑off voltage (Vrwm), assuming that values higher than operating voltage are sufficient. When surges arrive, the TVS turns on and clamps voltage to clamping voltage Vc. If this Vc exceeds the absolute maximum rated voltage of protected chips at the rear stage, chips are still exposed to breakdown risks. Therefore, under maximum peak pulse current conditions, TVS Vc must be strictly compared against the withstand‑voltage limit of subsequent circuits with adequate safety margin reserved.

3. Multi‑level Cooperative Protection Architecture

A single protective device cannot cover full‑band threats ranging from lightning surges to electrostatic discharge. Industrial‑grade protection requires layered protection strategies.

First stage: Primary protection (energy‑discharging layer). Gas discharge tubes (GDT) or metal‑oxide varistors (MOV) are commonly applied to dissipate high‑energy surges of thousands of amperes induced by lightning. These components feature relatively slow response speed and high residual voltage.

Second stage: Decoupling buffer (isolation layer). Constructed by resistors or inductors, it serves as the core link for coordinated protection. Impedance components produce voltage drop and time‑delay effects to slow down surge rising‑edge rate and limit transient energy flowing toward rear circuits. It effectively prevents component failure caused by response‑time mismatch between front‑stage and rear‑stage devices.

Third stage: Fine protection (voltage‑limiting layer). TVS diodes with picosecond‑level response accurately clamp residual voltage within safe ranges, providing final protection for sensitive rear‑end ICs.

4. PCB Layout: Protection Performance Degraded by Parasitic Parameters

The performance of protective components heavily depends on PCB layout. Parasitic inductance often offsets nominal component performance. According to electromagnetic induction law V = L·(di/dt), steep high‑current surges generate significant reverse induced voltage from parasitic inductance on component pins and grounding traces. Superimposed with clamping voltage, it threatens subsequent circuits. Hence, grounding pins of protective devices should connect directly to reference ground planes with shortest and widest traces. Routing through vias should be avoided. Moreover, all protective devices must be placed close to power input connectors, so surges can be dissipated immediately upon intrusion. Prevent surges from spreading for long distances inside PCB layers and coupling into adjacent sensitive signal traces.

DC input circuit protection is a systematic discipline covering material properties, thermal performance and electromagnetic compatibility. Designers shall accurately identify extreme operating conditions faced by equipment, properly match electrical‑parameter boundaries of each‑stage components, and minimize parasitic effects through rigorous PCB layout. Systematic pre‑planning and sufficient verification lay the foundation for reliable on‑site operation throughout the full product lifecycle.